The present invention relates to a switching control method for a level shifter, as well as to a self-controlled level shifter, particularly for standard CMOS technology low-power references. The invention relates, particularly but not exclusively, to a CMOS technology application, and in the detailed description which follows reference will be made to this field of application for convenience of illustration only.
As is well known, suitable transistors are not available to withstand a high potential across the drain-source junction, as well as at the gate terminal for devices used in low supply voltage processes. As a result, level shifters, e.g. of the cascode type, are usually used for transferring high voltage levels. In particular, VDDL denotes herein a nominal supply voltage level, in particular a low voltage level; VDDH denotes a high voltage level to be transferred; and VREF denotes a reference voltage level, needed to control the different steps of a generic cascode operation.
A conventional shifter of the cascode type is shown generally at 1 in FIG. 1, in schematic form. FIG. 1 illustrates schematically the generators, 2 and 3, respectively for the reference voltage VREF and the high voltage VDDH, only in terms of their operation. The generators 2 and 3 are driven by the same selection signal SEL.
The shifter 1 basically comprises a differential cell having an input section 4, comprising a first MOS transistor MN1 and a second MOS transistor MN2 and being connected to an input terminal IN of the shifter 1 and to a voltage reference, e.g. a ground reference GND. An output section 5, is also provided and comprises a third MOS transistor MP3 and a fourth MOS transistor MP4 and being connected to the input section 4, as well as to an output terminal OUT of the shifter 1 and to a reference node X, the latter receiving a reference voltage VREF. In addition, the shifter 1 also includes a biasing section 6, comprising a fifth MOS transistor MP5 and a sixth MOS transistor MP6 and being connected between the output section 5 and a high-voltage reference VDDH.
In particular, the first transistor MN1 of the input section 4 has a drain terminal connected to the output terminal OUT, a source terminal connected to ground GND, and a gate terminal connected to the input terminal IN through an inverter INV. A second transistor MN2 of the input section 4 has a drain terminal connected to a drain terminal of the fourth transistor MP4 of the output section 5, a source terminal connected to ground GND, and a gate terminal connected to the input terminal IN directly. Furthermore, the third transistor MP3 of the output section 5 has a source terminal connected to a first internal circuit node A, a drain terminal connected to the output terminal OUT of the shifter 1, and a gate terminal connected to the reference node X. The fourth transistor MP4 of the output section 5 has a source terminal connected to a drain terminal of the sixth transistor MP6 of the biasing section 6, a drain terminal connected to the drain terminal of the second transistor MN2 of the input section 4, and a gate terminal connected to the reference node X. Lastly, the fifth transistor MP5 of the biasing section 6 has a drain terminal connected to the first internal circuit node A, a source terminal connected to the high-voltage reference VDDH, and a gate terminal cross-connected to the drain terminal of the sixth transistor MP6. The latter has a source terminal connected to the high-voltage reference VDDH, and a gate terminal cross-connected to the drain terminal of the fifth transistor MP5, i.e. to the first internal circuit node A.
Thus, the third and fifth transistors MP3 and MP5, as well as the fourth and sixth transistors MP4 and MP6, are cascode connected. In particular, transistors MP3 and MP5 can be viewed as forming an output leg of the differential cell. The input terminal IN of the shifter 1 receives the selection signal SEL turning on the shifter, and also causing the generators 2, 3 to generate the voltage references VDDH and VREF. Finally, the second internal circuit node B is connected to an output terminal OUT of the shifter 1.
It will be now described what happens as the output terminal OUT is switched from a high voltage value VDDH over to a low voltage value VDDL, i.e. upon the high voltage VDDH being de-selected at the output terminal OUT. As shown schematically in FIGS. 2A to 2D, in a steady state, before the high voltage is de-selected at the output terminal OUT, i.e. within the time lapse from ta to tb shown in FIGS. 2A to 2D, the reference voltage VREF is a value such that the third transistor MP3 enters conduction. This is so while the potential differences between the gate and the drain terminals, |Vgd(MP3)|, and between the gate and the source terminals, |Vgs(MP3)|, of the third transistor MP3 are held below the highest admissible value, which is typically much lower than the high voltage value VDDH.
Therefore, the following relation applies generally:
VREF less than VAxe2x88x92|Vth(MP3)|
where VA is the voltage at the first internal circuit node A, and Vth(MP3) is the threshold voltage of the third transistor MP3.
Under these conditions, the gate terminal of the first transistor MN1 has a low voltage value, and will not interfere with transferring the high voltage VDDH to the output terminal OUT. Thus, the high voltage VDDH will be distributed through the cascoded branch comprising the third and fifth transistors, MP3 and MP5, so that the transistor oxides and junctions are not overly stressed.
The situation is similar, but reversed, in the branch comprising the fourth and the sixth transistors, MP4 and MP6. At a time tb, when the selection signal SEL goes low, the high voltage VDDH at the output terminal OUT decreases, and concurrently therewith, the level of the reference voltage VREF goes high (typically but not necessarily to VDDL). In this way, the stress for the transistors in the structure is attenuated and the level shifter 1 turned off completely.
However, the selection of the first transistor MN1, which takes place upon its gate terminal going high, i.e. as the signal SEL on the input terminal IN goes low, will pull the output terminal OUT quickly to ground. This may produce a voltage drop of similar magnitude across the node X due to the capacitive coupling of the gate-drain capacitance Cgd(MP3) and source-gate capacitance Cgs(MP3) of the third transistor MP3 (FIG. 1).
Actually, the value of the voltage variation occurring at the output terminal OUT (from VDDH to 0V) may even pull the node X to negative voltage values, with the reference voltage VREF at node X being a fairly low value, even during the previous high-voltage phase, as shown in FIG. 2C. This produces stress on the gate oxides and makes correctly biasing the transistors of the shifter 1 more difficult to achieve.
This capacitive effect becomes larger, the larger the load on the output terminal OUT, as when a number of shifters are connected in parallel to the same node. Also, the dimensions W of the transistors MP1 and MP3 are proportional to the load to be driven. Thus, the output terminal OUT will have increased inertia, and the coupling between the output terminal OUT and the node X of the reference voltage VREF will be boosted by the dimensional increase of the transistors in shifter 1, as shown diagrammatically in FIG. 2D. However, a steadier reference voltage VREF generally involves circulation of a large current through its bias circuit (not shown because it is conventional), resulting in undesired static power consumption and increased power dissipation of the device where the shifter 1 is integrated.
This prior approach, although effective, has an inherent limitation in the operation of de-selection of the high voltage VDDH at the output terminal OUT of the shifter 1, due to the capacitive effects of the node X whereat the reference voltage VREF is, as required for cascode operation. This problem becomes more acute, the higher the drive capability required to the level shifter, i.e. the larger the load to be handled by the shifter.
An embodiment of this invention is directed to a switching control method avoiding the lowering of the reference voltage VREF described hereinabove when the output node of the shifter is switched. This result is obtained without the use of high power biasing for the reference voltage VREF.
The control method drives the phase of de-selection of the shifter output node initially at a high voltage, to only trigger it in after a condition of minimum coupling to the reference node X, whereat the reference voltage VREF is established. In this way, a low-power type of reference generator, having a reduced drive capability and relatively simpler design, can be used for this reference voltage.
This is achieved in a substantially xe2x80x9cautomaticxe2x80x9d mode, i.e. with no need to provide additional external control signals. In particular, the control method allows the shifter to control itself. This is in the sense that it requires no external synchronization and employs an additional control circuit that comprises essentially a comparator driving a sequential circuit.
The switching control method comprises a phase of de-selection of a high voltage value at an output terminal of the shifter using a selection signal. The de-selection phase may comprise the following: starting the de-selection by bringing the selection signal to a low value; de-activating, by the selection signal, the generation of a high-voltage signal, being supplied to the shifter, and a reference voltage signal; computing the difference between an internal voltage signal of the shifter, and the reference voltage signal; generating a control signal when the calculated difference is found to be less than a threshold voltage value; and applying the selection signal to an input terminal of the shifter in the presence of the control signal.
Another embodiment is directed to an improved self-controlled shifter, of the cascode type just described. The shifter may comprise a differential cell including an input section receiving a selection signal at an input terminal; and an output section in cascode configuration and having a reference node arranged to receive a reference voltage signal. The output section may comprise at least one MOS transistor connected between an internal circuit node and the output terminal. The self-controlled shifter may comprise a switching control device having a first input terminal connected to the reference node, a second input terminal connected to the internal circuit node, a third input terminal receiving the selection signal, and an output terminal connected to the input terminal of the shifter to output a controlled switch signal to the input terminal of the shifter.